1. Field of the Invention
This invention relates to a system for providing communications between cores in an integrated circuit and, more particularly, to a reconfigurable circular bus.
2. Background of the Invention
A typical processing device includes various circuits such as a processor circuit, memory circuits, peripheral circuits, and the like. With recent technology, such a device may be manufactured using a printed circuit board supporting a plurality of integrated circuit chips. Each integrated circuit chip provided the functionality of one or more of the circuits. The individual circuits can be thought of as “core” circuits, or cores. When connected on a printed circuit board, the core circuits are often connected with point to point wiring.
More recently, system-on-a-chip (SOC) technology has been utilized. This technology is used, for example, in large ASICs (application specific integrated circuits) with many cores. The interconnection between cores becomes difficult due to wiring constraints and wiring congestion. A typical bus structure helps alleviate this problem by minimizing the wires between the various cores. Referring to FIG. 1, a block diagram for a typical SOC integrated circuit 10 is illustrated. The illustrative integrated circuit 10 includes six cores 12, 13, 14, 15, 16 and 17. Particularly, the cores 12, 13, 14, 15, 16 and 17 are identified under the letters A, B, C, D, E and F, respectively. Each of the cores 12–17 is connected to a data bus 18 and an address bus 20. This prior art structure limits the amount of bandwidth available for communication between the cores 12–17. All cores 12–17 share the same wires. As a result, only one pair of cores can communicate at the same time. The core connections may be tri-statable, or formed by ORing the gated outputs of all cores into one source driven back to all of the cores. Control of the buses 18 and 20 is granted by an arbiter (not shown) which grants control of the bus to one core at a time.
The present invention is directed to improvements in communication between cores in an integrated circuit.